HARDWARE-AWARE PERFORMANCE OPTIMIZATION OF YOLOV8 FOR REAL-TIME APPLICATIONS: GPU ACCELERATION WITH TENSORRT AND AN ANALYTICAL FPGA COMPARISON
DOI:
https://doi.org/10.5281/zenodo.20781147Abstract
Real-time computer-vision systems deployed on edge platforms are constrained as much by the surrounding software
pipeline and the host–accelerator interface as by raw compute. This paper presents a reproducible, hardware-aware optimization study
of the lightweight YOLOv8n object detector on an NVIDIA Tesla T4 GPU and contrasts the measured GPU behavior against an
analytical projection of a Xilinx Zynq UltraScale+ (ZU9EG) FPGA accelerator. Applying TensorRT graph optimization—vertical
Conv–BatchNorm–activation layer fusion together with FP16 precision—raised single-stream inference throughput on the T4 from a
PyTorch FP32 baseline of 62.92 FPS to 72.72 FPS, a 1.16× (15.6%) speed-up, while mean average precision on COCO val2017 fell
only marginally ([email protected] from 52.8% to 52.6%). A controlled batch-size sweep then exposes a host-side preprocessing bottleneck:
as the batch grows to 16, host CPU utilization saturates to 98%, while GPU utilization decreases to 8%, and end-to-end throughput
degrades to 2.05 effective FPS. We show analytically and empirically that this is a data-ingest (decode/resize) limitation of the host
pipeline rather than a compute limit of the accelerator. Finally, using device datasheets and published FPGA-accelerator figures, we
project that a spatial INT8 dataflow accelerator would deliver lower peak throughput (≈45 FPS) but markedly better energy efficiency
and deterministic per-frame latency, characteristics desirable for latency-critical edge deployment. All numerical claims are clearly
separated into measured (GPU) and projected (FPGA) categories.
Keywords
object detection; YOLOv8; TensorRT; layer fusion; FP16/INT8 quantization; GPU; FPGA; edge inference; energy efficiency; deterministic latency.References
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